1. Field of the Invention
The present invention relates to an apparatus for processing digital video data with an error correction parity, and in particular, to an apparatus for recording and reproducing or transmitting and receiving digital video data with an error correction parity, comprising error concealment means, such as a digital VTR, a digital video data transmitter, a receiver, a transceiver or the like.
2. Description of the Related Art
As video tape recording and reproducing apparatuses (referred to as VTRs hereinafter) each for encoding a video signal into digital video signal, recording the digital video signal onto a magnetic tape and reproducing the recorded digital video signal from the magnetic tape, the following VTRs have been put into practical use:
(a) D1-VTR which uses a component signal as a signal to be recorded; PA1 (b) D2-VTR which uses a composite signal as a signal to be recorded; and PA1 (c) D3-VTR. PA1 error correction means for correcting an error of said input N-bit digital video data, outputting error-corrected N-bit digital video data, and generating and outputting an error detection signal representing an error which can not be corrected; PA1 data combining means for converting said error-corrected N-bit digital video data outputted from said error correction means into M-bit digital video data by combining said each one sample of said higher-order-N-bit data and said plurality of samples of said lower-order-(M-N)-bit data included in said error-corrected N-bit digital video data so as to obtain said M-bit digital video data, and outputting converted M-bit digital video data; PA1 error classifying means for classifying said error detection signal into a first error detection signal representing an error of said each one sample of said higher-order-N-bit data and a second error detection signal representing an error of said plurality of samples of said lower-order-(M-N)-bit data; and PA1 error concealment means for performing an error concealment process for said converted M-bit digital video data outputted from said data combining means based on said first error detection signal outputted from said error classifying means. PA1 data dividing means for dividing each sample of input M-bit digital video data into high-order-N-bit data and lower-order-(M-N)-bit data, constituting each one sample of said higher-order-N-bit data as one symbol of a predetermined error correction code, constituting a plurality of samples of said lower-order-(M-N)-bit data as one symbol of the error correction code, and outputting N-bit digital video data including said each one sample of the higher-order-N-bit data and said plurality of samples of the lower-order-M-N)-bit data, M being a predetermined natural number, N being a predetermined natural number smaller than the natural number M; PA1 parity adding means for adding an error correction parity to said N-bit digital video data outputted from said data dividing means, and outputting said N-bit digital video data with said error correction parity; PA1 recording means for recording said N-bit digital video data with said error correction parity outputted from said parity adding means, onto a recording medium; PA1 reproducing means for reproducing said N-bit digital video data with said error correction parity recorded on said recording medium; PA1 error correction means for correcting an error of said N-bit digital video data outputted from said reproducing means, outputting error-corrected N-bit digital video data, and generating and outputting an error detection signal representing an error which can not be corrected; PA1 data combining means for converting said error-corrected N-bit digital video data outputted from said error correction means into M-bit digital video data by combining said each one sample of said higher-order-N-bit data and said plurality of samples of said lower-order-(M-N)-bit data included in said error-corrected N-bit digital video data so as to obtain said M-bit digital video data, and outputting converted M-bit digital video data; PA1 error classifying means for classifying said error detection signal into a first error detection signal representing an error of said each one sample of said higher-order-N-bit data and a second error detection signal representing an error of said plurality of samples of said lower-order-(M-N)-bit data; and PA1 error concealment means for performing an error concealment process for said converted M-bit digital video data outputted from said data coining means based on said first error detection signal outputted from said error classifying means. PA1 reproducing means for reproducing said N-bit digital video data with said error correction parity recorded on said recording medium; PA1 error correction means for correcting an error of said N-bit digital video data outputted from said reproducing means, outputting error-corrected N-bit digital video data, and generating and outputting an error detection signal representing an error which can not be corrected; PA1 data combining means for converting said error-corrected N-bit digital video data outputted from said error correction means into M-bit digital video data by combining said each one sample of said higher-order-N-bit data and said plurality of samples of said lower-order-(M-N)-bit data included in said error-corrected N-bit digital video data so as to obtain said M-bit digital video data, and outputting converted M-bit digital video data; PA1 error classifying means for classifying said error detection signal into a first error detection signal representing an error of said each one sample of said higher-order-N-bit data and a second error detection signal representing an error of said plurality of samples of said lower-order-(M-N)-bit data; and PA1 error concealment means for performing an error concealment process for said converted M-bit digital video data outputted from said data combining means based on said first error detection signal outputted from said error classifying means. PA1 parity adding means for adding an error correction parity to said N-bit digital video data outputted from said data dividing means, and outputting said N-bit digital video data with said error correction parity; PA1 transmitting means for transmitting said N-bit digital video data with said error correction parity outputted from said parity adding means, to a predetermined destination station; PA1 receiving means for receiving said N-bit digital video data with said error correction parity from said destination station; PA1 error correction means for correcting an error of said N-bit digital video data outputted from said receiving means, outputting error-corrected N-bit digital video data, and generating and outputting an error detection signal representing an error which can not be corrected; PA1 data combining means for converting said error-corrected N-bit digital video data outputted from said error correction means into M-bit digital video data by combining said each one sample of said higher-order-N-bit data and said plurality of samples of said lower-order-(M-N)-bit data included in said error-corrected N-bit digital video data so as to obtain said M-bit digital video data, and outputting converted M-bit digital video data; PA1 error classifying means for classifying said error detection signal into a first error detection signal representing an error of said each one sample of said higher-order-N-bit data and a second error detection signal representing an error of said plurality of samples of said lower-order-(M-N)-bit data and PA1 error concealment means for performing an error concealment process for said converted M-bit digital video data outputted from said data combining means based on said first error detection signal outputted from said error classifying means. PA1 receiving means for receiving said N-bit digital video data with said error correction parity from said destination station; PA1 error correction means for correcting an error of said N-bit digital video data outputted from said receiving means, outputting error-corrected N-bit digital video data, and generating and outputting an error detection signal representing an error which can not be corrected; PA1 data combining means for converting said error-corrected N-bit digital video data outputted from said error correction means into M-bit digital video data by combining said each one sample of said higher-order-N-bit data and said plurality of samples of said lower-order-(M-N)-bit data included in said error-corrected N-bit digital video data so as to obtain said M-bit digital video data, and outputting converted M-bit digital video data; PA1 error classifying means for classifying said error detection signal into a first error detection signal representing an error of said each one sample of said higher-order-N-bit data and a second error detection signal representing an error of said plurality of samples of said lower-order-(M-N)-bit data; and PA1 error concealment means for performing an error concealment process for said converted M-bit digital video data outputted from said data combining means based on said first error detection signal outputted from said error classifying means. PA1 line memory means for storing said error detection signal outputted from said error correction means, said line memory means having a memory capacity for storing said error detection signal of two horizontal scanning line; PA1 write memory control means for controlling said line memory means so as to write said error detection signal representing an error of said high-order-N-bit data into said line memory means; PA1 read memory control means for controlling said line memory means so as to read out and output said error detection signal as said first error detection signal.
The details of the D1-VTR are disclosed in, for example, "SMPTE 227M 19-mm type D1 cassette-helical data and control record", SMPTE Journal, March 1992. In the D1-VTR, a video signal is sampled according to the so-called 4:2:2 method, and then the sampled signal is quantized into eight-bit digital video data, which is recorded onto a magnetic tape having a width of 3/4 inches. In the 4:2:2 method, the luminance signal is sampled at 13.5 MHz, and the two color difference signals are sampled at 6.75 MHz, respectively.
In the D2-VTR, the composite video signal is sampled at the frequency which is four times the frequency of the subcarrier signal, and then the sampled signal is quantized into eight-bit video data, which is recorded onto a magnetic tape having a width of 3/4 inches. However, since the magnetic tape has the width of 3/4 inches, the D2-VTR can not be reduced in the size and weight thereof, and this is requested for a camera integrally incorporated type VTR. According to these needs in the markets, the D3-VTR was manufactured as a product. In the D3-VTR, the composite video signal is quantized into eight-bit video data, and the video data is recorded onto a magnetic tape having a width of 1/2 inches.
In these digital VTRs, an error correction code is made so that one sample obtained by sampling and quantizing an analog video signal so as to convert the same into digital video data of eight bits is used as one symbol of the error correction code. Then, an error concealment process for predicting the contents of an error sample is performed for a sample for which an error correction can not be performed, utilizing a correlation of the video signal.
On the other hand, in order to heighten the quality of image of digital video data used for digital VTRs, a digital VTR has been developed which samples and quantizes input analog video signal so as to convert the same into digital video data of ten bits.
For example, in the U.S. Pat. No. 4,730,223 as issued to Ikeda et al. (referred to as Ikeda et al. hereinafter), digital video data of ten bits obtained by quantizing an input analog video signal so as to convert the same into digital video data of ten bits is divided into higher-order-eight-bit data and lower-order-two-bit data and eight-bit data made of the lower-order-two-bit data in a unit of four pixels is produced. Then the eight-bit data made of the lower-order-two-bit data is arranged before or after one horizontal scanning line of the digital video data, thereby converting input digital video data of ten bits into digital video data of eight bits. The converted digital video data of eight bits is transmitted to a destination station through a communication line.
In Ikeda et al., there is mentioned a method for converting ten-bit digital video data into eight-bit digital video data, however, there is no mention in Ikeda et al. of any concealment process for error samples when an error occurs in a digital video data transmission.
FIG. 14 shows a conventional digital VTR for recording and reproducing digital video data of eight bits converted from input ten-bit-quantized digital video data, which is disclosed in Ikeda et al.
Referring to FIG. 14, the conventional digital VTR comprises an input terminal 1, a first data converting circuit 59, an error correction parity adding circuit 3, a recording processing circuit 4, a recording magnetic head 4a, a reproducing magnetic head 6a, a reproducing processing circuit 6, an error correction circuit 7, a second data converting circuit 60, an error concealment circuit 61, and an output terminal 11.
Ten-bit-quantized digital video data is inputted through the input terminal 1 to the first data converting circuit 59, which converts the input ten-bit digital video data into eight-bit digital video data. This data converting method is as follows. For example, the input ten-bit digital video data is divided into higher-order-eight-bit digital video data and lower-order-two-bit digital video data, and then, eight-bit digital video data made of the lower-order-two-bit digital video data in a unit of four pixels is produced. Thereafter, the eight-bit digital video data made of the lower-order-two-bit digital video data is added as the fifth data after the data made of the higher-order-eight-bit data, and then is inputted to the error correction parity adding circuit 3. In this case, M=10 and N=8. The error correction parity adding circuit 3 adds an error correction parity to the input digital video data, and outputs the digital video data with the error correction parity to the recording processing circuit 4. Then, the recording processing circuit 4 modulates a carrier signal according to the input digital video data using a predetermined modulation method and amplifies the modulated signal, and then outputs the modulated signal to the recording magnetic head 4a, which records the modulated signal outputted from the recording processing circuit 4 onto the magnetic tape 5.
On the other hand, the reproducing magnetic head 6a reproduces the modulated signal recorded on the magnetic tape 5, and the reproducing processing circuit 6 amplifies the modulated signal reproduced by the reproducing magnetic head 6a and demodulates the amplified signal so as to obtain reproduced digital video data, which is outputted to the error correction circuit 7. Then, the error correction circuit 7 performs an error correction process for the digital video data outputted from the reproducing processing circuit 6, and outputs the processed digital video data to the second data converting circuit 60, which performs an inverse process to the data converting process of the first data converting circuit 59, namely, converts the input eight-bit digital video data into ten-bit digital video data and outputs the converted ten-bit digital video data to the error concealment circuit 61. Thereafter, the error concealment circuit 61 performs an error concealment process for error samples using a correlation of the video signal, so as to interpolate a sample corresponding to the error sample, based on the peripheral error samples thereof, and outputs the error-concealed digital video data through the output terminal 11.
However, in the conventional digital VTR shown in FIG. 14, when the error correction of the eight-bit digital video data constituted by the lower-order-two-bits in a unit of four pixels can not be performed, all the four pixels are error-concealed by the error concealment circuit 61. Therefore, only one symbol error influences the digital video data of four pixels. In this case, any error may not occur in the higher-order-eight-bit data of the above-mentioned four pixels, and therefore, as a result of the error concealment process, the quality of image of output digital video data unfortunately deteriorates.